The present invention relates generally to a method and/or architecture to implement a multiple array memory device in a single die and, more particularly, to a dual SRAM in a single die with configurable sizes.
Conventional approaches for implementing two SRAM circuits implementing two individual SRAMs on more than one die. Implementing more than one die in an application such as a computer motherboard or other device takes up additional board space. Such a dual implementation also requires additional die space, increasing costs.
The present invention concerns a circuit generally comprising a memory and a logic circuit. The memory may comprise (i) a first section configured to (a) read and write data and (b) have a first configurable size and (ii) a second section configured to (a) read and write data independently of the first section and (b) have a second configurable size. The logic circuit may be configured to control the first configurable size and the second configurable size.
The objects, features and advantages of the present invention include providing a method and/or architecture that may implement (i) a configurable SRAM architecture, (ii) two or more dual independent SRAMs on a single die and/or (iii) a single circuit in applications that presently require two SRAMs.